https://doi.org/10.65770/TZMX1214
ABSTRACT
This paper presents the architecture, implementation, and evaluation of a high-throughput CubeSat communication signal recovery pipeline realized on the Xilinx Zynq-7000 System-on-Chip (SoC), specifically targeting the xc7z020clg400-1 device and developed within the Vivado 2021.2 integrated design environment. The principal design paradigm is Hardware-Software Co-Design, in which computationally intensive, latency-critical signal processing operations are offloaded onto the Programmable Logic (PL) fabric, while control-plane responsibilities are handled by the embedded dual-core ARM Cortex-A9 Processing System (PS), communicating via AXI4-Lite and AXI4-Stream bus interfaces. The PL signal chain comprises seven functionally distinct hardware modules: a signal generator, a multi-band selection matrix, a physics-motivated space-channel noise injector (LFSR-driven), a vendor-optimized 7-tap FIR lowpass filter, a bitwise gain scaling amplifier, a threshold-based hard-decision demodulator, and a synchronous Bit Error Rate (BER) monitoring core. Simulation and synthesis results demonstrate timing closure at 125 MHz, modest FPGA resource utilization (under 4% LUT usage), and a simulated BER improvement of approximately 8.9 dB post-filtering, rising to 12.4 dB with gain optimization, relative to the raw corrupted signal baseline. The work validates the viability of low-cost, resource-constrained SoC platforms for CubeSat on-board and ground-segment digital baseband processing.
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