ABSTRACT
This paper explores the capacitance and resistance modeling of 3-D (dimensional) SOI FinFET structure and circuit implementation approach is done for the utility of SOI FinFET structure. The scaling of the FinFET structure is continuously ongoing and increased parasitic and resistance affects the circuit level performance of SOI FinFET in ICs (Integrated Circuits) below 20 nm technology node. A geometrical-based analysis is done to get the optimized parasitic capacitance and resistance model and validity of the model is verified by three-dimensional (3-D) field solver Synopsys Raphael software. For utility of the developed model, some circuit implementation is done in h-spice simulation environment.
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